Low-Power, Low-Spurious 2.4GHz Subsampling PLL

A simulated low-power subsampled phase-locked loop (PLL) that addresses the reference branch affected by VCO load modulation during subsampling operations. It features a comprehensive analysis of binary frequency shift keying (BFSK) effects, with adaptive, low-noise, and low-power characteristics. Its applications include 5G or satellite communications, high-speed data converter clocks, and similar fields.

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Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur *highlight

Fully Digital Frequency Synthesizer for IoT Applications

A low-power fractional-n all-digital PLL (ADPLL) for narrowband IoT applications. Multi-step lock control and oscillator tuning word coarse prediction algorithms accelerate the locking process to under 20µs. The digital-to-time converter (DTC), when used with the phase prediction algorithm, minimizes the detection range of the low-power time-to-digital converter. It features high performance, low power consumption, small area, and reconfigurability. Application areas include narrowband IoT applications and 5G communications.

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A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

8-14 GHz Wideband Integer-N Frequency Divider Clock Chip

A wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO) is presented. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. 

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Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL

A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS

8-14 GHz / 23-42 GHz Wideband Fractional-N Frequency Divider Clock Chip

Wide frequency coverage phase-locked loops (PLLs) with high frequency resolution and low phase noise are one of the key components of high-speed communication systems. DTC/DAC-free and linearly calibrated PLLs have advanced advantages, and the proposed phase digitization scheme with intrinsically high linearity is optimized in more advanced process nodes.

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An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS