8-14 GHz Wideband Integer-N Frequency Divider Clock Chip

A wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO) is presented. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. 

Paper Link：

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL

A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS

8-14 GHz / 23-42 GHz Wideband Fractional-N Frequency Divider Clock Chip

Wide frequency coverage phase-locked loops (PLLs) with high frequency resolution and low phase noise are one of the key components of high-speed communication systems. DTC/DAC-free and linearly calibrated PLLs have advanced advantages, and the proposed phase digitization scheme with intrinsically high linearity is optimized in more advanced process nodes.

Paper Link：

An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS