2.4GHz Sub-Sampling Phase Locked Loop (PLL) of Low Phase Noise and Low Reference Spur

An analog low-power sub-sampling phase locked loop (PLL) that tackles the reference spur caused by VCO load modulation from the sub-sampling operation is presented, featuring adaptive, low noise and low power consumption. A complete analysis on the binary frequency shift keying (BFSK) effect including the impact of the VCO buffer is provided. Its application areas include 5G or satellite communication, high-speed data converter clocks, and more.

Paper Link：

Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur *The paper is a cover article

Fully Digital Frequency Synthesizer for IoT Applications

A low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications is presented, featuring high performance, low power consumption, small area, and reconfigurability. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less than 20μs. A digital-to-time converter (DTC) is used with a phase prediction algorithm to minimize the detection range of the time-to-digital converter for low power consumption. Application areas are narrowband IoT applications, 5G communications.

Paper Link：

A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

NB-IoT interference suppression transceiver front-end

An NB-IoT interference suppression method based on higher-order statistical characteristics is used to filter out interference signals by detecting whether the input signal contains interference signals and using the difference between these interference signals and NB-IoT signals in the higher-order statistical domain for adaptive filtering, which is characterized by low-power consumption, low-cost, low-noise, and reconfigurable. The application areas are IoT applications, 5G communications, wireless sensors, and narrowband receivers.

Multi-mode Ultra-low Power Wake-up Receiver

A multi-mode ultra-low power wake-up receiver based on direct envelope detection in HF/UHF band is analyzed and presented, featuring high sensitivity, low power consumption, and HF/UHF..  In order to balance the power consumption and sensitivity, multi-mode with power detection (PD), signal detection (SD), and high sensitivity signal detection (HSSD) are adopted.  The application areas include smart sensors, wireless sensor networks, the Internet of Things (IoT), and Wi-Fi applications.

Paper Link：

Analysis and Design of a Multi-Mode Wake-Up Receiver Based on Direct Envelope Detection in Wireless Sensor Networks