Education

September 2015–June 2019,  Fudan University,  Bachelor of Science in Microelectronics Science and Engineering

September 2019–June 2024,  Fudan University,  Doctor of Philosophy in Microelectronics and Solid-State Electronics

Work

Currently employed at Zhenhua Fengguang Semiconductor as a Research and Development Engineer, responsible for designing high-performance clocks and frequency synthesizers, as well as RF/mmWave/mixed-signal systems.

Research

Paper：

[1] T. Ou et al., A 0.06mm2 14.7-to-20.2GHz Quad-Core VCO Enabled by the Folded Circular Transformer Achieving 201.1dBc/Hz FoMT and 203.4dBc/Hz FoMA, 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025, pp. 1-3, doi: 10.23919/VLSITechnologyandCir65189.2025.11074803.

[2] Y. Wang et al., An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS, 2024 IEEE Custom Integrated Circuits Conference (CICC), Denver, CO, USA, 2024, pp. 1-2, doi: 10.1109/CICC60959.2024.10529006. 

[3] H. Xu, S. Ji, Y. Wang, X. Lin, H. Min and N. Yan, Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 8, pp. 3597-3607, Aug. 2024, doi: 10.1109/TCSI.2024.3380600.

[4] T. Zou et al., A 6–12 GHz Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 7, pp. 2802-2813, July 2023, doi: 10.1109/TCSI.2023.3267791.

[5] Y. Wang et al., Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL, in IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2252-2266, Aug. 2023, doi: 10.1109/JSSC.2023.3242617.

[6] T. Zou et al., A Capacitor Assisting Triple-Winding Transformer Low-Noise Amplifier with 0.8-1.5dB NF $6-12\text{GHz BW} \pm 0.75\text{dB}$ Ripple in 130nm SOI CMOS, 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, USA, 2022, pp. 231-234, doi: 10.1109/RFIC54546.2022.9862955. 

[7] S. Ji et al., A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM, in IEEE Microwave and Wireless Components Letters, vol. 32, no. 5, pp. 403-405, May 2022, doi: 10.1109/LMWC.2022.3149274.

[8] Y. Wang, T. Zou, B. Chen, S. Ji, C. Zhang and N. Yan, A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Republic of, 2021, pp. 1-3, doi: 10.1109/A-SSCC53895.2021.9634839.

Honors

Shanghai Outstanding Graduate

Rong Chang - Fudan Innovation Star

First Prize, Fudan University Doctoral Student Academic Excellence Scholarship

An Qiwei Scholarship Outstanding Award