Research

High-Speed Mixed-Signal Integrated Circuit Design

Education

September 2012–June 2016,  Bachelor of Science in Electronic Information Engineering, Hubei University of Arts and Science

September 2016–June 2019,  Master of Science in Circuits and Systems, Central China Normal University

September 2019–June 2023,  Ph.D. in Physics, Central China Normal University

June 2025–Present,  Postdoctoral Researcher in Integrated Circuit Science and Engineering, Fudan University

Achievements

Paper:

①Cong Zhao, Di Guo, et al. A 20 Gbps PAM4 VCSEL Driving ASIC for Detector Front-end Readout, Nuclear Instruments & Methods In Physics Research Section A

②Cong Zhao, Di Guo et al. A 25 Gbps VCSEL Driving ASIC: An Attempt for Ultra-High-Speed Front-end Readout Applications, JINST, 2022

③Cong Zhao, Di Guo et al. A 12-Channel 10 Gbps/ch VCSEL Driver ASIC in 55 nm CMOS for High Energy Physics Experiments，EI，2021

④Cong Zhao, Qiangjun Chen et al. A low noise 5.12 GHz PLL ASIC in 55 nm for NICA Multi-Purpose Detector Project，JINST，2022

⑤Cong Zhao, Qiangjun Chen et al. A 14 Gbps VCSEL Driving ASIC in 55 nm for NICA Multi -Purpose Detector Project，JINST，2022

Patent：

① 电流监控电路及激光器应用电路 ZL201910801031.X

② 基于电感峰化和前馈电容补偿的VCSEL激光器驱动电路ZL201822011415.5

③一种低压CMOS工艺的VCSEL激光器驱动电路ZL201822011269.6 

Honors

Huawei Cup Fifth China Graduate Student Innovation Competition National Second Prize

Introduction

Zhao Cong, Ph.D., graduated from Central China Normal University. His primary research focuses on high-speed, high-performance SerDes interface chip design and high-speed chip testing, covering data rates from 1Gbps to 25Gbps. This includes modules such as high-speed TX, RX, CTLE, FFE, PLL, CDR, and high-speed laser driver LDD. He has led and participated in five enterprise product mass production projects, all of which have achieved mass production and shipment. His hobbies include badminton and running.