【ISSCC】An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS

To satisfy the demand for high data rates and low clock jitter in next-generation ultra-high-speed wireline communication, the research team proposed an 8-phase clock generation circuit featuring ultra-wide operation bandwidth, low phase noise, and high phase accuracy. The proposed dual-feedback ring oscillator decouples the frequency generation loop from the phase synchronization loop, significantly enhancing the maximum oscillation frequency and operation bandwidth with a given process node. 8-phase clock signals generated by a wide-band delay-locked loop are injection locked to the ring oscillator, improving output phase accuracy without degrading phase noise. The proposed design achieves less than 38fs jitter and a phase error below 3° across an 8–28GHz output frequency, almost 100% improvement in frequency versus other 8-phase clock generators in more advanced technology nodes. It scales well in advanced technology and is particularly suitable for future generation high-speed wireline applications.

This multi-phase clock generator was developed by Yechen Tian who is currently a Ph.D. student at the School of Microelectronics, Fudan University. The corresponding authors are Professors Na Yan and Hao Xu from Fudan University. This work has been published at ISSCC 2025, a premier conference in the field of integrated circuits.