Wideband 8-14 GHz Fractional-Division Phase-Locked Loop with ADC Full-Domain Quantization

The research team proposes a fractional-division-type all-digital phase-locked loop (Frac-N ADPLL) with low noise and low spurious based on analog-to-digital converter (ADC) phase discrimination. Aiming at the difficulties of in-band noise suppression and fractional spurious cancellation in conventional fractional-type phase-locked loops, a high-gain, high-linearity, and high-dynamic-range phase discriminator based on a linear time-to-voltage converter and an analog-to-digital converter is proposed, as well as an all-digital-domain fractional-quantization noise cancellation technique. The inherent linear conversion characteristic of the proposed discriminator eliminates noise folding and reduces fractional spuriousness, avoids complex linearity calibration circuits, and realizes fractional frequency synthesis with low noise and low spuriousness. The phase-locked loop chip is realized in a 40nm CMOS process, and achieves broadband frequency synthesis from 8 to 14 GHz with a power consumption of 20mW. The integration jitter in integer and fractional modes is less than 160 fs and 180 fs, respectively, and the in-band (100kHz frequency deviation) fractional spurious level is less than -57dBc.

The results were published in 2024 CICC, the top international conference on integrated circuits, with Yizhuo Wang, a doctoral student at School of Microelectronics, Fudan University, as the first author.

Ppaer Link：

Y. Wang et al., An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS, 2024 IEEE Custom Integrated Circuits Conference (CICC), Denver, CO, USA, 2024, pp. 1-2, doi: 10.1109/CICC60959.2024.10529006.