26-32 GHz High Precision High Linearity Attenuator

The research team proposes an attenuator based on the parallel capacitor phase compensation technique. By analyzing the transfer function of the circuit in detail, the compensation capacitor introduced in this design achieves zero-pole cancellation, thus reducing the phase and attenuation errors over a wide bandwidth range. By quantitatively analyzing the switch size of the series branch and the impedance ratio of the parallel branch and optimizing the design, the design elucidates the mutual constraints of insertion loss, bandwidth, and linearity, and proposes a design methodology that can quickly converge to the boundaries of the optimal metrics, which greatly reduces the iterative time required for the design. Meanwhile, based on the EKV model, the team analyzed the linearity of the attenuator unit and proposed an optimized cascade order of the attenuator unit, which breaks through the problem of poor linearity of traditional CMOS attenuators. The designed attenuator is fabricated in a 40nm CMOS process and achieves an attenuation range of 0-31.5dB in 0.5dB steps over a bandwidth of 26-32GHz. The attenuator achieves an RMS attenuation/phase error of less than 0.23dB/5.58° and an IP1dB greater than 11.2dBm in a compact area (0.124mm²).

The relevant results were published in TMTT, a top IC journal, with An Sun, a doctoral student at the School of Microelectronics, Fudan University, as the first author.

Paper Link：

A. Sun et al., A 26–32-GHz CMOS Attenuator With Optimized Capacitive Compensation and High Linearity Enhancement, in IEEE Transactions on Microwave Theory and Techniques, doi: 10.1109/TMTT.2024.3515134.