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Sub-Sampling Type Phase-Locked Loop Spurious Noise Suppression Technique
发布时间：2025-01-20
The periodic interference of the subsampling phase discriminator on the voltage-controlled oscillator is the main source of spurious limitation of the subsampling type phase-locked loop, to address this problem, the research team established a model of the nonlinear modulation effect of the subsampling phase discriminator on the voltage-controlled oscillator, and put forward a cascaded high isolation phase detector embedded in a linear capacitor, which realizes the simultaneous suppression of the phase-locked loop output spuriousness and noise. For the limitation of high power consumption of frequency lock loop in subsampling phase-locked loop, the team proposes a self-starting frequency lock loop that can monitor the loop lock state in real time, which significantly reduces the power consumption of the chip. A phase-locked loop chip with 2.4 GHz output, 185 fs integral jitter, -72 dBc spurious, and 1.1 mW power consumption was finally realized in a 40 nm CMOS process, and the results were published in the IEEE Transactions on Circuits and Systems - I: Regular Papers (TCAS-Papers), 2024, and the results were published in the IEEE Transactions on Circuits and Systems - I: Regular Papers (TCAS-Papers), 2024. The results were published in the 2024 IEEE Transactions on Circuits and Systems - I: Regular Papers (TCAS-I), and were recognized as the August 2024 Highlight Paper.
The paper was co-authored by Xu Hao, a young researcher at the School of Microelectronics, and Ji Shujiang, a doctoral student, and other students, and the first author of the paper is Xu Hao, and the corresponding author is Yan Na.
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