1. A 16.5–31.6 GHz Broadband Bidirectional Front-End
The research team presents a broadband bidirectional front-end operating from 16.5 GHz to 31.6 GHz for emerging millimeter-wave applications, including 5G/6G communications, low-Earth-orbit (LEO) satellite systems, and joint communication and sensing (JCAS). The proposed architecture employs a reused matching network (RMN) that integrates transmit/receive switching, impedance matching, and LNA gm-boosting without requiring an antenna-side switch, thereby reducing insertion loss and chip area. A coupling-polarity-reversal switch (CPRS) is introduced to enhance TX/RX isolation, while an adaptive-bias (ADB) circuit improves transmitter linearity. In addition, a magnetically-electrically coupled resonator (MECR) is utilized to achieve broadband low-noise performance in the receiver. Fabricated in a 40-nm CMOS process, the prototype occupies a compact core area of only 0.21 mm² and achieves a continuous 16.5–31.6 GHz 3-dB bandwidth. In TX mode, it delivers 16.4 dB gain, 16.5 dBm saturated output power (Psat), 16.1 dBm output 1-dB compression point (OP1dB), and a peak power-added efficiency (PAE) of 27%. In RX mode, it achieves 14.6 dB gain, a 4.8–6.2 dB noise figure (NF), and a maximum input 1-dB compression point (IP1dB) of −4.8 dBm. The proposed front-end demonstrates an efficient, compact, and high-linearity solution for next-generation broadband millimeter-wave transceivers.
This work was presented at the 2026 IEEE Radio Frequency Technology and Techniques Symposium (RFTT 2026), with Zhipu Luo as the first author from Fudan University.
Paper:Z. Luo, J. Gu, H. Qin, X. He, K. Hu, K. Han, H. Xu, and N. Yan, “A 16.5–31.6 GHz Broadband Bidirectional Front-end with 16.1 dBm OP1dB and 26.8% PAE@OP1dB in 40 nm Bulk CMOS,”in Proceedings of the IEEE Radio Frequency Technology and Techniques Symposium (RFTT), Boston, MA, USA, Jun. 2026.


2. A 17–32 GHz Bidirectional Amplitude–Phase Control Circuit for Multibeam Phased Array Transceivers in 40-nm CMOS
The research team presents a 17–32 GHz bidirectional amplitude–phase control (Bi-APC) circuit for multibeam phased-array transceivers. For amplitude control, the design employs a bidirectional variable-gain amplifier (BVGA) combined with an attenuator to achieve wide-range, high-precision, and low-loss amplitude control. Bidirectional operation is efficiently enabled by symmetric three-stage amplification paths and reused transformers, while a resistor-capacitor feedback (RCFB) technique is introduced in the inter-stage matching networks to enhance gain flatness. In terms of phase control, the team adopts a passive vector-modulation phase shifter (PVMPS), which utilizes C-R-C isolation and differential inductive coupling to reduce the passive area of the power combiner and enhance high-frequency performance. In addition, segmented control words alleviate the quadrature imbalance of the coupler across the frequency band, achieving wideband phase control with low error.
Fabricated in a 40-nm CMOS process, the chip features a compact core area of 0.54 mm². Measurement results show that the chip supports 17–32 GHz bidirectional amplitude and phase control, offering a tuning range and resolution of 31.5 dB / 360° and 0.5 dB / 5.625°, respectively, with an RMS error of less than 0.46 dB / 2.6°. It achieves peak gains of 3.3 dB in the receive (RX) direction and 1.7 dB in the transmit (TX) direction. The noise figure (NF) in the RX direction is below 7.3 dB, and the output 1-dB compression point (OP1dB) in the TX direction exceeds 6 dBm, with an overall power consumption of 29.7mW.
This work was presented at the 2026 IEEE MTT-S RF Technology & Techniques (RFTT) Symposium, with Jialiang Sun, a master's student from Fudan University, as the first author.
Paper: J. Sun et al., A 17–32 GHz Bidirectional Amplitude–Phase Control Circuit for Multibeam Phased Array Transceivers in 40-nm CMOS, 2026 IEEE MTT-S RF Technology & Techniques (RFTT) Symposium - RFTT 2026, Boston, MA, USA.

