A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization

The research team proposes a fractional-N digital frequency synthesizer architecture operating from 24 to 42 GHz. The proposed phase detector (PD) consists of a sampling current integrator cascaded with a charge-redistribution successive-approximation register analog-to-digital converter (SAR ADC). It fully captures the Σ-Δ fractional quantization noise to enable all-digital noise cancellation. Benefiting from inherently linear time-to-digital conversion, the PLL achieves state-of-the-art performance without nonlinearity calibration. Supplied with a 100 MHz reference clock, the synthesizer employs injection locking of two LC frequency triplers, delivering an output frequency range of 23.4–42.1 GHz with integrated jitter less than 180 fs.

This work was published in the 2026 issue of the IEEE Journal of Solid-State Circuits (JSSC), a top SCI journal in the Chinese Academy of Sciences Journal Ranking Q1. Research Fellow Xu Hao from the School of Microelectronics, Fudan University, serves as the first author.

Paper：Xu H, Wang Y, Jiao Z, et al. A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization[J]. IEEE Journal of Solid-State Circuits ( Early Access ), 2026. DOI:10.1109/jssc.2026.3671094.