A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving −269.9-dB FoMJitter-N-Area

The research team proposes a compact-area digital ring PLL for chiplet applications. The complete power spectral density of the pulse-shaper-based PLL is derived and verified. Using the comprehensive loop transfer function, the loop bandwidth can be optimized while maintaining loop stability. This optimization effectively suppresses the phase noise of the ring oscillator, achieving an integrated jitter performance of 804 fs. With nonlinearity cancellation and digital offset compensation, the range-extension constant-slope digital time converter (DTC) maintains high linearity, yielding a fractional spur of −53.2 dBc near integer channels. Operating at 6.8 GHz, the PLL achieves a high power efficiency of 0.83 mW/GHz. Benefiting from the small footprint of the ring oscillator and range-extension DTC, the prototype occupies a core area of only 0.025 mm², with a FoMJitter-N-Area of −269.9 dB.

This work was published in the 2026 issue of IEEE Transactions on Circuits and Systems I (TCAS-I). Dr. Gao Haoyuan from the School of Microelectronics, Fudan University, is the first author.

Paper：Gao, H., Liu, Y., Wu, P., Liu, J., Mao, Y., Lin, X., Yin, R., Lu, P., Kong, L., & Yan, N. (2026). A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving −269.9-dB FoMJitter-N-Area. IEEE Transactions on Circuits and Systems. I, Regular Papers, 73(4), 2425–2437. https://doi.org/10.1109/TCSI.2025.3628957.