2024
Wang, Y., Xu, H., Li, G., Liu, S., Liu, Y., Yin, R., Pan, H., & Yan, N. (2024). An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS. 2024 IEEE Custom Integrated Circuits Conference (CICC), 1–2.
Xu, H., Bi, J., Zou, T., He, W., Zeng, Y., Gu, J., Jiao, Z., Liu, S., Zhu, Z., & Yan, N. (2024). 5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 67, 88–90.
Qin, H., Gu, J., Xu, H., Xu, Z., Jia, P., & Yan, N. (2024). A 25-31GHz Compact True Power Detector with >33dB Dynamic Range in 40nm Bulk CMOS. 2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 135–138.
Gao, H., Liu, Y., Wu, P., Liu, J., Mao, Y., Lin, X., & Yan, N. (2024). A 6.8GHz -269.9 FOMJitter-N-Area Fractional-N Pulse Shaper Based PLL with Range Extension DTC. 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 697–700.
Sun, A., Qin, H., Xu, H., & Yan, N. (2024). A Compact 0.1-19.7GHz Ultra-Wideband Power Amplifier with ±0.5dB Gain Ripple in 28 nm CMOS Process. 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 388–391.
Wang, L., Han, K., Xu, H., Yin, R., & Yan, N. (2024). A 20.6 to 30.5 GHz Two Stage Cascode LNA in 40nm CMOS for Phase Array Tranceiver. 2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024, 1–3.
Liu, F., Wang, L., Zhang, S., Zhang, H., & Yan, N. (2024). A Fixed-Peak-Current Single-Inductor-Multiple-Output DC-DC Converter Achieving 92.6% Peak Efficiency. IEEE International Conference on Solid-State and Integrated Circuit Technology (Online), 1–3.
He, W., Zeng, Y., Jia, B., Min, H., Xu, H., & Yan, N. (2024). A 47μW Wake-Up Receiver with -77dBm Sensitivity Using a Mixer-First Architecture. IEEE International Conference on Solid-State and Integrated Circuit Technology (Online), 1–3.